Power semiconductor devices are semiconductor elements that withstand high voltage and high current, and preferably have low loss. Power semiconductor devices have recently been used in the form of high-speed inverters. When the power semiconductor devices are used in such a manner, a need exists for high-speed operation.
A silicon (Si) semiconductor is used as a material of the power semiconductor devices. Meanwhile, in recent years, attention has been directed toward power semiconductor devices of silicon carbide (SiC), and development for such power semiconductor devices is underway.
The dielectric breakdown voltage of silicon carbide itself is an order of magnitude higher than that of silicon. For this reason, when a power semiconductor device is fabricated using silicon carbide, a reverse voltage can be maintained even in a situation where a depletion layer at the pn junction or at the Schottky junction is thin. Thus, a high-breakdown-voltage and low-loss power semiconductor device having low on-resistance can be achieved by reducing the device thickness and increasing the doping concentration of a silicon carbide layer. The saturated electron velocity of silicon carbide is about twice as high as that of silicon. Thus, high-speed operation can be achieved.
Examples of power semiconductor devices of silicon carbide include a planar-type metal-insulator-semiconductor field-effect transistor (hereinafter abbreviated as MISFET). The planar-type MISFET typically includes an n−-type epitaxial layer having p-type body regions each including an n+-type source region. The source region forms ohmic contact with a source electrode. A region of the n−-type epitaxial layer surrounding each body region forms a junction field-effect transistor (JFET) region. The source electrode has the same potential as the body region.
Preferably, in a planar-type MISFET, a change in potential of a body region instantaneously follows a change in potential of a source electrode. If the contact resistance between the source electrode and the body region is high, a delay unfortunately occurs after the potential of the source electrode changes and until the potential of an end portion of the body region changes. Such a potential change delay causes a delay in switching time, and is significantly problematic for power semiconductor devices requiring a higher operating speed.
To reduce the contact resistance between a source electrode and a body region of a planar-type MISFET, the body region includes a contact region heavily doped with p-type impurities, and the source electrode and the body region are electrically connected together through the contact region (see, for example, PATENT DOCUMENT 1).
It has been examined to allow the contact region to have an impurity profile in which the impurity concentration in the depth direction is substantially fixed, i.e., a box profile. To further reduce the contact resistance between the source electrode and the contact region, a method has been studied in which after impurities have been implanted into a silicon carbide semiconductor layer, the surface of the silicon carbide semiconductor layer is removed by, e.g., hydrogen etching to allow the peak of the impurity concentration to be in the vicinity of the surface of the contact region (see, for example, PATENT DOCUMENT 2).